View MT90401AB1_1285352.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

MT90401 SONET/SDH System Synchronizer
Data Sheet Features
* * * Meets requirements of GR-253-CORE for SONET Stratum 3 and SONET minimum clock Meets requirements of GR-1244-CORE Stratum 3 Meets requirements of G.813 Option 1 and Option 2 for SDH Equipment Clocks (SEC) with external jitter attenuator Provides OC-3/STM-1, DS3, E3, 19.44 MHz, DS2, E1, T1, 8 kHz and ST-BUS clock outputs Accepts reference inputs from two independent sources Selectable 1.544 MHz, 2.048 MHz, 19.44 MHz or 8kHz input reference frequencies Holdover accuracy of 0.02 ppm Adjustable output clock phase supporting masterslave arrangements Hardware or microprocessor control (8 bit microprocessor interface) 3.3 V supply JTAG boundary scan Ordering Information MT90401AB 80 Pin LQFP MT90401AB1 80 Pin LQFP* *Pb Free Matte Tin -40C to +85C Trays Trays
January 2005
* * * * * * * *
Applications
* * * * SONET/SDH Add/Drop multiplexers SONET/SDH uplinks Integrated access devices ATM edge switches
Description
The MT90401 is a digital phase locked loop (DPLL) that is designed to synchronize SDH (Synchronous Digital Hierarchy) and SONET (Synchronous Optical Network) networking equipment. The MT90401 is used to ensure that the timing of outgoing signals remains within the limits specified by Telcordia, ANSI and the ITU during normal operation and in the presence of disturbances on the incoming synchronization signals.
LOCK VDD VSS
TCLR
C20i TCK TDI TMS TRST TDO PRI SEC Prioor Secoor
Master Clock
IEEE 1149.1a
TIE Corrector Circuit Selected Reference TIE Corrector Enable Reference Select
Virtual Reference DPLL Output Interface Circuit State Select Input Impairment Monitor
Reference Select MUX
Reference Monitor
State Select
C155P/N C19o C1.5o C2o C4o C6o C8o C16o C44/C34 F0o F8o F16o
Feedback Frequency Select MUX
RSEL
Control State Machine
RST MS1 MS2 HOLDOVER PCCi FLOCK D0/D7 A0/A6 CS,DS,R/W
FS1
FS2
Figure 1 - Functional Block Diagram 1
Zarlink Semiconductor Inc. Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc. Copyright 2003-2005, Zarlink Semiconductor Inc. All Rights Reserved.
MT90401
Data Sheet
The MT90401 can operate in free-run, locked or holdover mode. The loop filter corner frequency can be selected to suit SONET applications or to suit SDH applications. The MT90401 uses an external 20 MHz oscillator as its master clock and it does not require external loop filter components. In Hardware Mode, the MT90401 can be controlled and monitored via external pins. In Microport Mode, a microprocessor can be used for more comprehensive control and monitoring.
IC DS FLOCK LOCK PCCi HOLDOVER VDD4 C34/C44 VSS7 C20i NC VDD3 TCLR RSEL C19o VSS5 IC C6o C1.5o PRIOOR 60 62 64 36 66 34 68 32 70 72 28 74 26 76 24 78 22 80 2 4 6 8 10 12 14 16 18 20 58 56 54 52 50 48 46 44 42 40 38
SECOOR OE CS RST HW D0 D1 D2 D3 VSS8 IC IC VDD5 D4 D5 D6 D7 R/W A0 IC
MT90401AB
30
FS1 FS2 Tdi Trst Tclk Tms Tdo VREF VSS4 C155P C155N VDD VDD2 VSS3 IC VSS2 PRI SEC E3/DS3 E3DS3/OC3
IC A1 A2 A3 A4 VSS9 A5 A6 SONET/SDH VDD1 VSS1 F16o C16o C8o C4o C2o F0o
Figure 2 - Pin Connections 80 Pin LQFP for MT90401
2
Zarlink Semiconductor Inc.
MS1
MS2 F8o
MT90401
Pin Description Pin # 1 2-5 6 7, 8 9 Name IC A1 - A4 VSS9 A5, A6 Description Internal Connection. Leave unconnected.
Data Sheet
Address 1 to 4 (5 V tolerant Inputs). Address inputs for the parallel processor interface. Digital ground. 0 Volts Address 5, to 6 (5 V tolerant Input). Address inputs for the parallel processor interface.
SONET/SD SONET/SDH (Input). In hardware mode set this pin high to have a loop filter corner H frequency of 70 millihertz and limit the phase slope to 885 ns per second. Set this pin low to have a corner frequency of approximately 1.1 hertz and limit the phase slope to 53 ns per 1.326 ms. This pin performs no function if the device is not in hardware mode. VDD1 VSS1 F16o Positive Power Supply. Digital supply. Digital ground. 0 Volts Frame Pulse ST-BUS 8.192 Mb/s (CMOS Output). This is an 8kHz 61ns active low framing pulse, which marks the beginning of an ST-BUS frame. This is typically used for STBUS operation at 8.192 Mb/s. Clock 16.384 MHz (CMOS Output). This output is used for ST-BUS operation with a 16.384 MHz clock. Clock 8.192 MHz (CMOS Output). This output is used for ST-BUS operation at 8.192 Mb/s. Clock 4.096 MHz (CMOS Output). This output is used for ST-BUS operation at 2.048 Mb/s and 4.096 Mb/s. Clock 2.048 MHz (CMOS Output). This output is used for ST-BUS operation at 2.048 Mb/s. Frame Pulse ST-BUS 2.048 Mb/s (CMOS Output). This is an 8 kHz 244 ns active low framing pulse, which marks the beginning of an ST-BUS frame. This is typically used for STBUS operation at 2.048 Mb/s and 4.096 Mb/s. Mode/Control Select 1 (Input). This input, together with MS2, determines the state (Normal, Holdover, or Freerun) of operation. See Table 3 on page 15. The logic level at this input is gated in by the rising edge of F8o. This pin performs no function if the device is not in hardware mode. Mode/Control Select 2 (Input). This input, together with MS1, determines the state (Normal, Holdover or Freerun) of operation. See Table 3 on page 15. The logic level at this input is gated in by the rising edge of F8o. This pin performs no function if the device is not in hardware mode. Frame Pulse Generic (CMOS Output). This is an 8 kHz 122 ns active high framing pulse, which marks the beginning of a TDM frame. This is typically used for TDM streams operating at 8.192 Mb/s.
10 11 12
13 14 15 16 17
C16o C8o C4o C2o F0o
18
MS1
19
MS2
20
F8o
21
E3DS3/OC3 E3DS3 or OC-3 Selection (Input). In Hardware Mode a low on this pin enables the differential 155.52 MHz output clock on the C155N/C155P pins; this will also cause the C34/C44 pin to output its nominal clock frequency divided by 4. In Hardware Mode, a high on this pin disables the differential 155.52 MHz output clock on the C155N/C155P pins; this will also cause the C34/C44 pin to output its nominal clock frequency. This pin performs no function if the device is not in Hardware Mode.
3
Zarlink Semiconductor Inc.
MT90401
Pin Description (continued) Pin # 22 Name E3/DS3 Description
Data Sheet
E3 or DS3 Selection (Input). In Hardware Mode a low on this pin selects a clock rate of 44.736 MHz for the C34/C44 pin, while a high selects a clock rate of 34.368 MHz. This pin performs no function if the device is not in hardware mode. Secondary Reference (Input). This is one of two (PRI & SEC) input reference sources (falling edge) used for synchronization. One of four possible frequencies ( 8kHz, 1.544 MHz, 2.048 MHz or 19.44 MHz) may be used. In hardware mode the selection of the input reference is based upon the MS1, MS2 and RSEL control inputs. Primary Reference (Input). This is one of two (PRI & SEC) input reference sources (falling edge) used for synchronization. One of four possible frequencies (8 kHz, 1.544 MHz, 2.048 MHz or 19.44 MHz) may be used. In hardware mode the selection of the input reference is based upon the MS1, MS2 and RSEL control inputs. Digital ground. 0 Volts Internal Connection. Leave unconnected Analog ground. 0 Volts Positive Analog Power Supply. Analog supply. Positive Power Supply. Digital supply. LVDS 155.52 MHz (Output)). Differential outputs generating a 155.52 MHz clock Digital ground. 0 Volts LVDS Reference Voltage (Input). IEEE 1149.1a Test Data Output (Output). If not used, this pin should be left unconnected. IEEE 1149.1a Test Mode Selection (Input). If not used, this pin should be pulled high. IEEE 1149.1a Test Clock Signal (Input). If not used, this pin should be pulled high. IEEE 1149.1a Reset Signal (Input). If not used, this pin should be held low. IEEE 1149.1a Test Data Input (Input). If not used, this pin should be pulled high. Frequency Select 2 (Input). This input, in conjunction with FS1, selects which of four possible frequencies (8 kHz, 1.544 MHz, 2.048 MHz or 19.44 MHz) may be input to the PRI and SEC inputs. For more details see FS2 bit description in Table 6 - Control Register 1 (Address 00H - Read/Write). Frequency Select 1 (Input). This input, in conjunction with FS2, selects which of four possible frequencies (8 kHz, 1.544 MHz, 2.048 MHz or 19.44 MHz) may be input to the PRI and SEC inputs. For more details see FS1 bit description in Table 6 - Control Register 1 (Address 00H - Read/Write). Primary Reference Out Of Range (CMOS Output). A logic high at this pin indicates that the primary reference is off the PLL center frequency by more than 12 ppm. The measurement is done on a 1 second basis using a signal derived from the 20 MHz clock input on C20i. When the accuracy of the 20 MHz clock is 4.6 ppm, the effective out of range limits of the PRIOOR signal will be +16.6 ppm to -7.4 ppm or +7.4 ppm to -16.6 ppm. Clock 1.544 MHz (CMOS Output). This output is used in T1 applications. Clock 6.312 MHz (CMOS Output). This output is used for DS2 or J2 applications. Internal Connection. Tie low for normal operation.
23
SEC
24
PRI
25 26 27 28 29 30 31 32 33 34 35 36 37 38 39
VSS2 IC VSS3 VDD2 VDD C155N, C155P VSS4 VREF Tdo Tms Tclk Trst Tdi FS2
40
FS1
41
PRIOOR
42 43 44
C1.5o C6 IC
4
Zarlink Semiconductor Inc.
MT90401
Pin Description (continued) Pin # 45 46 47 Name VSS5 C19o RSEL Digital ground. 0 Volts Description
Data Sheet
Clock 19.44 MHz (CMOS Output). This output is used in OC-N and STM-N applications. Reference Source Select (Input). A logic low selects the PRI (primary) reference source as the input reference signal and a logic high selects the SEC (secondary) input. The logic level at this input is gated in by the rising edge of F8o. For more details see RSEL bit description in Table 6 - Control Register 1 (Address 00H - Read/Write). TIE Circuit Clear (Input). A logic low at this input clears the Time Interval Error (TIE) correction circuit resulting in a realignment of output phase with input phase. The TCLR pin should be held low for a minimum of 300 ns. When this pin is held low, the time interval error correction circuit is disabled. Positive Power Supply. Digital supply. No Connection. 20 MHz Clock Input (5 V tolerant Input). This pin is the input for the master 20 MHz clock. Digital ground. 0Volts Controlled Clock 34.368 MHz / Clock 44.736 MHz (CMOS Output). This output clock is programmable to be either 34.368 MHz (for E3 applications) or 44.736 MHz (for DS3 applications). The output clock is controlled via control pins in Hardware Mode or control bits when the device is in Microport Mode. If the E3DS3/OC3 control pin or control bit is high, the C34/C44 pin will output its nominal frequency. If the E3DS3/OC3 control pin or bit is low, the C34/C44 pin will output its nominal frequency divided by 4. (C8.5o/C11o)
48
TCLR
49 50 51 52 53
VDD3 NC C20i VSS7 C34/C44
54 55 56
VDD4 PCCi
Positive Power Supply. Digital supply. Phase Continuity Control Input (3 V Input). The signal at this pin affects the state changes between Primary Holdover Mode and Primary Normal Mode and Primary Holdover Mode and Secondary Normal Mode. The logic level at this input is gated by the rising edge of F8o. See Figure 12, "Control State Diagram" on page 21 for details. Lock Indicator (CMOS Output). This output goes high when the PLL is in frequency lock to the input reference. Fast Lock Mode (Input). In hardware mode, hold this pin high to lock faster than normal to the input reference. This pin performs no function if the device is not in hardware mode. In Fast Lock Mode, the wander generation of the PLL is, of necessity, compromised. Data Strobe (5 V tolerant Input). This input is the active low data strobe of the Motorola processor interface. Internal Connection. Tie low for normal operation. Secondary Reference Out Of Capture Range (CMOS Output). A logic high at this pin indicates that the secondary reference is off the PLL center frequency by more than 12 ppm. The measurement is done on a 1 second basis using a signal derived from the 20 MHz clock input on the C20i pin. When the accuracy of the 20 MHz clock is 4.6 ppm the effective out of range limits of the SECOOR signal will be +16.6 ppm to -7.4 ppm or +7.4 ppm to -16.6 ppm.
HOLDOVER Holdover (CMOS Output). This output goes high when the device is in holdover mode.
57 58
LOCK FLOCK
59 60 61
DS IC SECOOR
5
Zarlink Semiconductor Inc.
MT90401
Pin Description (continued) Pin # 62 63 Name OE CS Description
Data Sheet
Output Enable (Input). Tie high for normal operation. Tie low to force output clocks pins F16, F8, C16, C8, C4, C2 to a high impedance state. Chip Select (5 V tolerant Input). This active low input enables the non-multiplexed Motorola parallel microprocessor interface of the MT90401. When CS is set to high, the microprocessor interface is idle and all bus I/O pins will be in a high impedance state. RESET (5 V tolerant Input). This active low input puts the MT90401 in a reset condition. RST should be set to high for normal operation. The MT90401 should be reset after powerup and after the selected reference frequency is changed. The RST pin must be held low for a minimum of 1msec. to reset the device properly. Hardware Mode (Input). If this pin is tied low, the device is in microport mode and is controlled via the microport. If it is tied high, the device is in hardware mode and is controlled via the control pins MS1, MS2, FS1, FS2, FLOCK and SONET/SDH. Data 0 to Data 3 (5 V tolerant Three-state I/O). These signals combined with D4-D7 form the bidirectional data bus of the parallel processor interface (D0 is the least significant bit). Digital ground. 0 Volts. Internal Connection. Tie low for normal operation. Internal Connection. Tie low for normal operation. Positive Power Supply. Digital supply. Data 4 to Data 7 (5 V tolerant Three-state I/O). These signals combined with D0-D3 form the bidirectional data bus of the parallel processor interface (D7 is the most significant bit). Read/Write Select (5 V tolerant Input). This input controls the direction of the data bus D[0:7] during a microprocessor access. When R/W is high, the parallel processor is reading data from the MT90401. When low, the parallel processor is writing data to the MT90401. Address 0 (5 V tolerant Input). Address input for the parallel processor interface. A0 is the least significant input. Internal Connection. Tie low for normal operation.
64
RST
65
HW
66-69 70 71 72 73 74-77 78
D0 - D3 VSS8 IC IC VDD5 D4 - D7 R/W
79 80
A0 IC
6
Zarlink Semiconductor Inc.
MT90401 Table of Contents
Data Sheet
1.0 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 1.1 Reference Select MUX Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 1.2 Frequency Select MUX Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 1.3 Time Interval Error (TIE) Corrector Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 1.4 Digital Phase Lock Loop (DPLL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 1.5 Output Interface Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 1.6 Input Impairment Monitor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 1.7 State Machine Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 1.8 Master Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.0 Control and Mode of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.1 Normal Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.2 Holdover Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.3 Freerun Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.4 Fast Lock Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.5 Transitions from Freerun Mode or Holdover Mode to Normal Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.0 MT90401 Measures of Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.1 Jitter Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.2 Jitter Tolerance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.3 Jitter Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.4 Frequency Accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.5 Holdover Accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.6 Capture Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.7 Lock Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.8 Phase Slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.9 Frequency Slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.10 Time Interval Error (TIE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.11 Maximum Time Interval Error (MTIE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.12 Phase Continuity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.13 Phase Lock Time. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 4.0 MT90401 and Network Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5.0 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5.1 Master Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5.2 TIE Correction (using PCCi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5.3 C155 clock generation and LVDS output drivers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 5.4 Microport . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 5.5 Output Phase Adjustment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
7
Zarlink Semiconductor Inc.
MT90401 List of Figures
Data Sheet
Figure 1 - Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Figure 2 - Pin Connections 80 Pin LQFP for MT90401 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Figure 3 - TIE Corrector Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Figure 4 - DPLL Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Figure 5 - Output Interface Circuit Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Figure 6 - Control State Machine Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Figure 7 - Jitter Tolerance GR-1244 1.544 MHz Reference. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Figure 8 - Jitter Tolerance ITU-T G.813 Option 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Figure 9 - Jitter Tolerance SONET Category II (OC1) 19.44 MHz Input Reference. . . . . . . . . . . . . . . . . . . . . . . . 18 Figure 10 - Jitter and Wander Transfer with SONET filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Figure 11 - Jitter and Wander Transfer with SDH Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Figure 12 - Control State Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Figure 13 - LVDS Voltage Offset Vos Generation Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Figure 14 - Timing Parameter Measurement Voltage Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Figure 15 - Microport Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Figure 16 - Input to Output Timing for T1/E1 signals (Normal Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Figure 17 - Input to Output Timing for 19.44 MHz Signal (Normal Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Figure 18 - Output Timing 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Figure 19 - Output Timing 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Figure 20 - Input Controls Setup and Hold Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Figure 21 - Output Timing 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
8
Zarlink Semiconductor Inc.
MT90401 List of Tables
Data Sheet
Table 1 - Frequency Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Table 2 - Input Reference Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Table 3 - Operating Modes and States. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Table 4 - Control State Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Table 5 - Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Table 6 - Control Register 1 (Address 00H - Read/Write) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Table 7 - Status Register 1 (Address 01H - Read Only). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Table 8 - Control Register 2 (Address 04H - Read/Write) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Table 9 - Set Delay Word 2 (Address 06H - Read/Write). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Table 10 - Set Delay Word 1 (Address 07H - Read/Write). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Table 11 - Identification Word (Address 0FH - Read Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
9
Zarlink Semiconductor Inc.
MT90401
1.0 Functional Description
Data Sheet
The MT90401 is a SONET/SDH System Synchronizer, providing timing (clock) and synchronization (frame) signals to interface circuits for Digital Telecommunications Transmission links. Figure 1 is a functional block diagram which is described in the following sections.
1.1
Reference Select MUX Circuit
The MT90401 accepts two simultaneous reference input signals and operates on their falling edges. Either the primary reference (PRI) signal or the secondary reference (SEC) signal can be selected as input to the TIE Corrector Circuit. The selection is based on the Control, Mode and Reference Selection of the device. See Table 1 and Table 4.
1.2
Frequency Select MUX Circuit
The MT90401 operates with one of four possible input reference frequencies (8 kHz, 1.544 MHz, 2.048 MHz or 19.44 MHz). The frequency select inputs, FS1 and FS2, which come from pins in hardware mode and control bits in microport mode determine which of the four frequencies may be used at the reference inputs (PRI and SEC). Both inputs must have the same frequency applied to them. A reset (RST) must be performed after every frequency select input change. See Table 1 - Input Frequency Selection. FS2 0 FS1 0 Input Frequency 19.44 MHz
See FS2 and FS1 bit description in Table 6 - Control Register 1 (Address 00H - Read/Write)
0 1 1
1 0 1
8 kHz 1.544 MHz 2.048 MHz
Table 1 - Frequency Selection
1.3
Time Interval Error (TIE) Corrector Circuit
The TIE corrector circuit, when enabled, prevents a step change in phase on the input reference signals (PRI or SEC) from causing a step change in phase at the input of the DPLL block of Figure 1. During reference input rearrangement, such as during a switch from the primary reference (PRI) to the secondary reference (SEC), a step change in phase on the input signals will occur. A phase step at the input of the DPLL would lead to unacceptable phase changes in the output signal. As shown in Figure 3, the TIE Corrector Circuit receives one of the two reference (PRI or SEC) signals, passes the signal through a programmable delay line, and uses this delayed signal as an internal virtual reference, which is input to the DPLL. Therefore, the virtual reference is a delayed version of the selected reference. During a switch from one reference to the other, the State Machine first changes the mode of the device from Normal to Holdover. In Holdover Mode, the DPLL no longer uses the virtual reference signal, but generates an accurate clock signal using storage techniques. The Compare Circuit then measures the phase delay between the current phase (feedback signal) and the phase of the new reference signal. This delay value is passed to the Programmable Delay Circuit (See Figure 3). The new virtual reference signal is now at the same phase position as the previous reference signal would have been if the reference switch had not taken place. The State Machine then returns the device to Normal Mode.
10
Zarlink Semiconductor Inc.
MT90401
TCLR Resets Delay Control Circuit Control Signal
Data Sheet
Delay Value
PRI or SEC from Reference Select Mux
Programmable Delay Circuit
Virtual Reference to DPLL Compare Circuit
TIE Corrector Enable from State Machine
Feedback Signal from Frequency Select MUX
Figure 3 - TIE Corrector Circuit The DPLL now uses the new virtual reference signal, and since no phase step took place at the input of the DPLL, no phase step occurs at the output of the DPLL. In other words, reference switching will not create a phase change at the input of the DPLL, or at the output of the DPLL. Since internal delay circuitry maintains the alignment between the old virtual reference and the new virtual reference, a phase error may exist between the selected input reference signal and the output signal of the DPLL. This phase error is a function of the difference in phase between the two input reference signals during reference rearrangements. Each time a reference switch is made, the delay between input signal and output signal will change. The value of this delay is the accumulation of the error measured during each reference switch. The programmable delay circuit can be reset to zero by applying a logic low pulse to the TIE Circuit Clear (TCLR) pin. A minimum reset pulse width is 300 ns. This results in a phase realignment between the input reference signal and the output signal as shown in Figure 16. The speed of the phase alignment correction is limited to 885 ns/s in SONET mode and 53 ns per 1.326 ms in SDH mode, convergence is in the direction of least phase travel. The state diagram of Figure 12 indicates the state changes for which the TIE Corrector Circuit is activated.
11
Zarlink Semiconductor Inc.
MT90401
1.4 Digital Phase Lock Loop (DPLL)
Data Sheet
As shown in Figure 4, the DPLL of the MT90401 consists of a Phase Detector, Phase Slope Limiter, Loop Filter, Digitally Controlled Oscillator, and a Control Circuit.
Virtual Reference from TIE Corrector
Phase Detector
Phase Slope Limiter
Loop Filter
Digitally Controlled Oscillator
DPLL Reference to Output Interface Circuit
Feedback Signal from Frequency Select MUX
State Select from Input Impairment Monitor
Control Circuit
State Select from State Machine
Figure 4 - DPLL Block Diagram Phase Detector - the Phase Detector compares the virtual reference signal from the TIE Corrector circuit with the feedback signal from the Frequency Select MUX circuit, and provides an error signal corresponding to the phase difference between the two. This error signal is passed to the Phase Slope Limiter circuit. The Frequency Select MUX allows the proper feedback signal to be externally selected (e.g., 8 kHz, 1.544 MHz, 2.048 MHz or 19.44 MHz). Phase Slope Limiter - the Phase Slope Limiter receives the error signal from the Phase Detector and ensures that the DPLL responds to all input transient conditions with a limited output phase slope. In SONET Mode the maximum output phase slope is limited to 885 ns/s as per Telcordia GR-253-CORE. In SDH Mode the maximum output phase slope is 53 ns per 1.326 ms. Loop Filter - the Loop Filter is a low pass filter, that defines the network jitter and wander transfer requirements for all input reference frequencies (8 kHz, 1.544 MHz, 2.048 MHz, or 19.44 MHz). In SONET mode the loop filter has a cut-off frequency of 70 mHz to comply with Telcordia GR-253-CORE and GR-1244-CORE. In SDH mode the loop filter has a cut-off frequency of 1.1Hz to comply with ITU-T G.813 Option 1 and GR-1244-CORE. Control Circuit - the Control Circuit uses status and control information from the State Machine and the Input Impairment Circuit to set the mode of the DPLL. The three possible modes are Normal, Holdover and Freerun. Digitally Controlled Oscillator (DCO) - the DCO receives the limited and filtered signal from the Loop Filter, and based on its value, generates a corresponding digital output signal. The synchronization method of the DCO is dependent on the state of the MT90401. In Normal Mode, the DCO provides an output signal which is frequency and phase locked to the selected input reference signal. In Holdover Mode, the DCO is free running at a frequency equal to the last locked frequency the DCO was generating while in Normal Mode. In order to improve accuracy of the Holdover Mode the actual frequency sample is taken 30 to 60 ms before switching into holdover. In Freerun Mode, the DCO is free running with an accuracy equal to the accuracy of the C20i 20 MHz source. Telcordia GR-253-CORE requires that, during recovery from holdover, SONET clocks not change their output frequency at a rate faster than 2.9 ppm per second. In SONET Mode the MT90401 limits the rate of change of its output frequency (frequency slope) to less than 1.9ppm per second; this limit remains in place when the PLL is in Fast Lock Mode.
12
Zarlink Semiconductor Inc.
MT90401
Data Sheet
Lock Indicator - If the PLL is in frequency lock (frequency lock means the center frequency of the PLL is identical to the line frequency), and the input phase offset is small enough such that no phase slope limiting is exhibited, then the lock signal will be set high.
1.5
Output Interface Circuit
The output of the DCO (DPLL) is used by the Output Interface Circuit to provide the output signals shown in Figure 5. The Output Interface Circuit uses five Tapped Delay Lines in MT90401 followed by a T1 Divider Circuit, an E1 Divider Circuit, a DS2 Divider Circuit, and a x4/x8 PLL, to generate the required output signals. Five tapped delay lines are used to generate 8.592 MHz, 11.184 MHz, 16.384 MHz, 12.352 MHz, 12.624 MHz and 19.44 MHz signals. The E1 Divider Circuit uses the 16.384 MHz signal to generate four clock outputs and three frame pulse outputs. The C8o, C4o and C2o clocks are generated by simply dividing the C16o clock by two, four and eight respectively. These outputs have a nominal 50% duty cycle. The frame pulse outputs (F0o, F8o, and F16o) are generated directly from the C16 clock. The T1 Divider Circuit uses the 12.352 MHz signal to generate C1.5o. This output has a nominal 50% duty cycle. The DS2 Divider Circuit uses the 12.624 MHz signal to generate the clock output C6o. This output has a nominal 50% duty cycle. The 19.44 MHz signal is output on the C19o pin and it is multiplied by an internal PLL to generate the 155.52 MHz clock output on the C155P/N pins. The C155P/N clock has a nominal 50% duty cycle. The 8.592 MHz and 11.184 MHz signals are multiplied by an internal PLL to generate the 34.368 MHz or 44.736 MHz clock output on the C34/C44 pin. If the internal PLL is dedicated to the C155P/N clock then the C34/C44 pin will output the 8.592 MHz or 11.184 MHz clocks. The 34.368 Mhz and 44.736 MHz clocks have a nominal 50% duty cycle. The duty cycles of the 8.592 MHz and 11.184 MHz signals are dependent on the duty cycle of the 20 MHz clock input to the C20i pin.
13
Zarlink Semiconductor Inc.
MT90401
Data Sheet
12MHz Tapped Delay Line
T1 Divider
C1.5o
From DPLL
Tapped Delay Line
16MHz
E1 Divider
C2o C4o C8o C16o F0o F8o F16o
Tapped Delay Line
12MHz
DS2 Divider
C6o
Tapped Delay Line
19MHz
C19o
Tapped Delay Line
x4 / x8 PLL
C155P/N
8.5/11.2MHz
C34/C44
Figure 5 - Output Interface Circuit Block Diagram The T1 and E1 signals are generated from a common DPLL signal. Consequently, all frame pulses and clock outputs are locked to one another for all operating states, and are also locked to the selected input reference in Normal Mode. See Figure 18. All frame pulses and clock outputs have limited driving capability, and should be buffered when driving capacitive loads exceeding 30 pF.
1.6
Input Impairment Monitor
This circuit monitors the input signal to the DPLL and automatically enables the Auto-Holdover when the frequency of the incoming signal is outside the Auto-Holdover capture range. (See Performance Characteristics - Mode Switching). This includes a complete loss of incoming signal, or a large frequency shift in the incoming signal. When the incoming signal returns to normal, the DPLL is returned to Normal Mode with the output signal locked to the input signal. The holdover output signal in the MT90401 is based on the incoming signal 30 ms (minimum) to 60 ms prior to entering the Holdover Mode. The amount of phase drift while in holdover is negligible because the Holdover Mode is very accurate (i.e., 0.02 ppm). Consequently, the phase delay between the input and output after switching back to Normal Mode is preserved.
14
Zarlink Semiconductor Inc.
MT90401
1.7 State Machine Control
Data Sheet
An internal state machine can be enabled to control the TIE Corrector Circuit as shown in Figure 1. In hardware mode, control is based on the logic levels at the control inputs RSEL, MS1, MS2 and PCCi (See Figure 6). In Microport mode, control is based on the state of control bits RSEL, MS1 and MS2 and the PCCi pin. When switching from Primary Holdover to Primary Normal, the TIE Corrector Circuit is enabled when PCCi = 1, and disabled when PCCi = 0. All state machine changes occur synchronously on the rising edge of F8o. See the Control and Mode of Operation section for full details.
To Reference Select MUX To TIE Corrector Enable Control State Machine To DPLL State Select PCCi
RSEL
MS1
MS2
Figure 6 - Control State Machine Block Diagram
1.8
Master Clock
The MT90401 uses an external oscillator as the master timing source. For recommended master timing circuits, see the Applications - Master Clock section.
2.0
Control and Mode of Operation
The MT90401 has three possible modes of operation, Normal, Holdover and Freerun. In hardware mode the Mode/Control Select pins MS2 and MS1 select the mode and method of control as shown in Table 3. RSEL 0 1 Input Reference PRI SEC
Table 2 - Input Reference Selection
MS2 0 0 1 1
MS1 0 1 0 1
Mode NORMAL HOLDOVER FREERUN Reserved
Table 3 - Operating Modes and States The active reference input (PRI or SEC) is selected by the RSEL pin as shown in Table 2. Refer to Table 4 and Figure 12 for details of the state change sequences.
15
Zarlink Semiconductor Inc.
MT90401
2.1 Normal Mode
Data Sheet
Normal Mode is typically used when a slave clock source, synchronized to the network is required. In Normal Mode, the MT90401 provides timing and frame synchronization signals, which are synchronized to one of two reference inputs (PRI or SEC). The input reference signal may have a nominal frequency of 8 kHz, 1.544 MHz, 2.048 MHz or 19.44 MHz. The selection of input references is control dependent as shown in state table 4. The reference frequencies are selected by the frequency control pins/bits FS2 and FS1 as shown in Table 1.
2.2
Holdover Mode
Holdover Mode is typically used when network synchronization is temporarily disrupted. In Holdover Mode, the MT90401 provides timing and synchronization signals, which are not locked to an external reference signal, but are based on storage techniques. The storage value is determined while the device is in Normal Mode and locked to an external reference signal When in Normal Mode, and locked to the input reference signal, a numerical value corresponding to the MT90401 output reference frequency is stored alternately in two memory locations every 30 ms. When the device is switched into Holdover Mode, the value in memory from between 30 ms and 60 ms is used to set the output frequency of the device. The frequency accuracy of Holdover Mode is 0.02 ppm, which translates to a worst case 14 frame (125 us) slips in 24 hours. This is better than the Telcordia GR-1244-CORE Stratum 3 requirement of 0.37 ppm (255 frame slips per 24 hours). Two factors affect the accuracy of Holdover Mode. One is drift on the Master Clock and the other is jitter on the reference signal. The drift on the Master Clock oscillator propagates unattenuated and causes the same drift on the output clocks. This drift can only be reduced by selecting more stable Master Clock oscillator. For example, a 4.6 ppm temperature compensated clock oscillator may have a temperature coefficient of 0.03 ppm per degree C. The 10 degC change while in Holdover Mode, will result in an additional offset in frequency accuracy equal to 0.3ppm which is much greater than the internal holdover accuracy of the MT90401 (0.02 ppm). The other factor affecting accuracy is large jitter on the reference input prior (30 ms to 60 ms) to the mode switch. For instance, jitter of 7.5 UI at 700 Hz may reduce the Holdover Mode accuracy from 0.02 ppm to 0.10 ppm.
2.3
Freerun Mode
Freerun Mode is typically used when a master clock source is required, or immediately following system power-up before network synchronization is achieved. In Freerun Mode, the MT90401 provides timing and synchronization signals which are based on the master clock frequency (C20i) only, and are not synchronized to the reference signals (PRI and SEC). The accuracy of the output clock is equal to the accuracy of the master clock (C20i). So if a 20 ppm output clock is required, the master clock must also be 20 ppm. See Applications - Master Clock section.
2.4
Fast Lock Mode
Fast Lock Mode is a submode of Normal Mode, it is used to allow the MT90401 to lock to a reference eight times more quickly than normal. Fast Lock Mode necessarily compromises the wander generation characteristics of the MT90401. When the MT90401 is in Fast Lock Mode and SONET Mode at the same time, the PLL frequency slope is limited to less than 1.9 ppm per second.
16
Zarlink Semiconductor Inc.
MT90401
2.5 Transitions from Freerun Mode or Holdover Mode to Normal Mode
Data Sheet
Telcordia GR-253-CORE requires SONET Internal Clocks to settle within 100 s after transitioning from Freerun Mode or Holdover Mode to Normal Mode. During such a transition, the wander filtering requirements for a SONET Internal Clock are relaxed to make a 100 s settling time possible. To meet the GR-253-CORE 100 s settling time requirement at power-up and during a transition from Freerun Mode to Normal Mode the MT90401 should be placed in its SDH Mode until lock is achieved. When the PLL indicates lock the MT90401 should be placed in SONET Mode. During a transition from Holdover Mode to Normal Mode, GR-253-CORE requires a SONET Internal Clock to limit the frequency slope to less than 2.9 ppm per second. To meet the 100 s settling time during such a transition it is necessary to keep the MT90401 in SONET Mode and Fast Lock Mode until lock is achieved. When the PLL indicates lock the MT90401 can be taken out of its Fast Lock Mode. A transition from Holdover Mode to Normal Mode can result in a large initial frequency offset, for example 4.6 ppm, between the clock's reference and its output. The 2.9 ppm per second frequency slope limit required by GR-253-CORE places a lower limit on the time it takes for a SONET Internal Clock to acquire a new frequency. While the clock is acquiring the new frequency a phase error will accumulate which could cause the clock's settling time to be longer than 100 s. GR-1244-CORE and GR-253-CORE allow a clock to ignore some of the phase error accumulated during the transition from Holdover Mode to Normal Mode. During a transition from Holdover Mode to Normal Mode, if the MT90401 has not achieved lock within 16 seconds, it is recommended that the PLL be put briefly into its Holdover Mode and then returned to Normal Mode by toggling the MS1 pin or the MS1 control bit. Toggling the PLL into and out of Holdover will clear any accumulated phase error and reduce the settling time.
3.0
MT90401 Measures of Performance
The following are some synchronizer performance indicators and their corresponding definitions.
3.1
Jitter Generation
Jitter generation is the amount of jitter produced by a PLL and is measured at its output. It is measured by applying a reference signal with no jitter to the input of the device, and measuring its output jitter. Jitter generation may also be measured when the device is in a non-synchronizing mode, such as free running or holdover, by measuring the output jitter of the device. Jitter generation is usually measured with various band-limiting filters depending on the applicable standards.
3.2
Jitter Tolerance
Jitter tolerance is a measure of the ability of a PLL to operate properly (i.e., remain in lock and or regain lock in the presence of large jitter magnitudes at various jitter frequencies) when jitter is applied to its reference. The applied jitter magnitude and jitter frequency depends on the applicable standards (see Figures 7, 8 and 9).
17
Zarlink Semiconductor Inc.
MT90401
Data Sheet
Figure 7 - Jitter Tolerance GR-1244 1.544 MHz Reference
Figure 8 - Jitter Tolerance ITU-T G.813 Option 1
Figure 9 - Jitter Tolerance SONET Category II (OC1) 19.44 MHz Input Reference
3.3
Jitter Transfer
Jitter transfer or jitter attenuation refers to the magnitude of jitter at the output of a device for a given amount of jitter at the input of the device. Input jitter is applied at various amplitudes and frequencies, and output jitter is measured with various filters depending on the applicable standards. For the MT90401, two internal elements determine the jitter attenuation. This includes the low pass loop filter and the phase slope limiter. Both of these parameters have different settings depending on whether the device is in
18
Zarlink Semiconductor Inc.
MT90401
Data Sheet
SONET or SDH mode. For SONET mode the loop filter has a corner frequency of 70 millihertz and the output phase slope is limited to 885 ns per second. For SDH mode the loop filter has a corner frequency of 1.1 Hertz and a maximum phase slope of 53 ns per 1.326 milliseconds. If the input signal exceeds this rate, such as for very large amplitude low frequency input jitter, the maximum output phase slope will be limited. The MT90401 has ten outputs that can be locked to four possible input frequencies for a total of 40 possible jitter transfer functions. Since all outputs are derived from the same internal signal, the jitter transfer values for the four cases, 8 kHz to 8 kHz, 1.544 MHz to 1.544 MHz, 2.048 MHz to 2.048 MHz 19.44 MHz to 19.44 MHz can be applied to all outputs.
Figure 10 - Jitter and Wander Transfer with SONET filter
Figure 11 - Jitter and Wander Transfer with SDH Filter It should be noted that 1 UI at 1.544 MHz is 648 ns, which is not equal to 1 UI at 2.048 MHz, which is 488 ns. Consequently, a transfer value using different input and output frequencies must be calculated in common units (e.g., seconds) as shown in the following example. Example: What is the T1 and E1 output jitter when the T1 input jitter is 20UI (T1 UI Units) and the T1 to T1 jitter attenuation is 18 dB?
19
Zarlink Semiconductor Inc.
MT90401
- A ----- 20
Data Sheet
OutputT1 = InputT1 x10 OutputT1 = 20 x10 - 18 ------- 20
= 2.5UI ( T1 )
( 1UIT1 ) OutputE1 = OutputT1 x --------------------( 1UIE1 ) ( 644ns ) OutputE1 = OutputT1 x ------------------- = 3.3UI ( T1 ) ( 488ns ) Using the above method, the jitter attenuation can be calculated for all combinations of inputs and outputs based on the four jitter transfer functions provided. Since intrinsic jitter generation is always present, jitter attenuation will appear to be lower for small input jitter signals than for large ones. Consequently, accurate jitter transfer function measurements are usually made with large input jitter signals (e.g., 75% of the specified maximum jitter tolerance).
Description Input Controls MS2 0 0 0 0 0 1 MS1 0 0 0 1 1 0 RSEL 0 0 1 0 1 X PCCi 0 1 X X X X Freerun S0 S1 S1 S2 / / Normal (PRI) S1 S2 MTIE S1H S2H S0
State Normal (SEC) S2 S1 MTIE S1 MTIE / S2H S0 / S0 Holdover (PRI) S1H S1 S1 MTIE S2 MTIE Holdover (SEC) S2H S1 MTIE S1 MTIE S2 MTIE / S0
Legend: No Change / Not Valid MTIE State change occurs with TIE Corrector Circuit Refer to Control State Diagram for state changes to and from Auto-Holdover State
Table 4 - Control State Table
20
Zarlink Semiconductor Inc.
MT90401
Data Sheet
S0 Freerun (10X)
PCCi-0 PCCi-1
S1 Normal Primary (000)
{A
S1A Auto-Holdover Primary
S2A Auto-Holdover Secondary
{A}
S2 Normal Secondary (001)
(PCCi=0) (PCCi=1)
S1H Holdover Primary (010)
S2H Holdover Secondary (011)
NOTES: (XXX) MS2 MS1 RSEL {A} Invalid Reference Signal Movement to Normal State from any state requires a valid input signal Phase Re-Alignment Phase Continuity Maintained (without TIE Corrector Circuit) Phase Continuity Maintained (with TIE Corrector Circuit)
In the case where 19.44 MHz input reference clocks are selected (FS2,FS1 = 00) the MT90401 may latch inaccurate phase reading during transition between states: S1A>>S1 and S2A>>S2 which may cause frequency step exceeding 4.6 ppm and longer than 100 sec lock time.
Figure 12 - Control State Diagram
3.4
Frequency Accuracy
Frequency accuracy is defined as the absolute tolerance of an output clock signal when it is not locked to an external reference, but is operating in a free running mode. For the MT90401, the Freerun accuracy is equal to the Master Clock (C20i) accuracy.
3.5
Holdover Accuracy
Holdover accuracy is defined as the absolute tolerance of an output clock signal, when it is not locked to an external reference signal, but is operating using storage techniques. For the MT90401, the storage value is determined while the device is in Normal Mode and locked to an external reference signal. The initial frequency offset of the MT90401 in Holdover Mode is +20 x 10-9. This is more accurate than Telcordia's GR-1244-CORE stratum 3 requirements of +50 x 10-9. Once the MT90401 has transitioned into Holdover Mode, holdover stability is determined by the stability of the 20 MHz Master Clock Oscillator. The absolute Master Clock (C20i) accuracy of the MT90401 does not affect Holdover accuracy, but the change in C20i accuracy while in Holdover Mode does.
21
Zarlink Semiconductor Inc.
MT90401
3.6 Capture Range
Data Sheet
Also referred to as pull-in range. This is the input frequency range over which the synchronizer must be able to pull into synchronization. The MT90401 capture range is equal to 52 ppm minus the accuracy of the master clock (C20i). For example, a 32 ppm master clock results in a capture range of 20 ppm. MT90401 provides two pins and two bits, PRIOOR and SECOOR, to indicate whether the primary and secondary reference are within the 12 ppm of the nominal frequency. When the accuracy of the 20 MHz oscillator is 4.6 ppm the effective out of range limits of the PRIOOR and SECOOR pins will be +16.6 ppm to -7.4 ppm or +7.4 ppm to -16.6 ppm. Both references are monitored at the same time. PRIOOR and SECOOR are updated every 1.0 to 1.5 seconds.
3.7
Lock Range
This is the input frequency range over which the synchronizer must be able to maintain synchronization. The lock range is equal to the capture range for the MT90401.
3.8
Phase Slope
Phase slope is measured in seconds per second and is the rate at which a given signal changes phase with respect to an ideal signal. The given signal is typically the output signal. An ideal signal is one that is at exactly the nominal frequency and is completely free of jitter and wander.
3.9
Frequency Slope
Frequency slope is measured in ppm per second and is the rate at which the fractional frequency offset of a given signal changes. The fractional frequency offset is calculated with respect to an ideal signal. The given signal is typically the output signal. An ideal signal is one that is at exactly the nominal frequency and is completely free of jitter and wander.
3.10
Time Interval Error (TIE)
TIE is the time delay between a given timing signal and an ideal timing signal.
3.11
Maximum Time Interval Error (MTIE)
MTIE is the maximum peak to peak delay between a given timing signal and an ideal timing signal within a particular observation period. MTIE ( S ) = TIEmax ( t ) - TIEmin ( t )
3.12
Phase Continuity
Phase continuity is the phase difference between a given timing signal and an ideal timing signal at the end of a particular observation period. Usually, the given timing signal and the ideal timing signal are of the same frequency. Phase continuity applies to the output of the synchronizer after a signal disturbance due to a reference switch or a mode change.
22
Zarlink Semiconductor Inc.
MT90401
3.13 Phase Lock Time
Data Sheet
This is the time it takes the synchronizer to phase lock to the input signal. Phase lock occurs when the input signal and output signal are not changing in phase with respect to each other (not including jitter). Lock time is very difficult to determine because it is affected by many factors which include: 1. initial input to output phase difference 2. initial input to output frequency difference 3. synchronizer loop filter 4. synchronizer limiter Although a short lock time is desirable, it is not always possible to achieve due to other synchronizer requirements. For instance, better jitter transfer performance is achieved with a lower frequency loop filter which increases lock time. And better (smaller) phase slope performance (limiter) results in longer lock times. The MT90401 loop filter and limiter were optimized to meet the GR-253-CORE, GR-1244-CORE, and G-813 jitter transfer and phase slope requirements.
4.0
MT90401 and Network Specifications
The MT90401 meets all applicable PLL requirements for the following specifications. 1. Telcordia GR-1244-CORE December 2000 for Stratum 3, SONET Minimum Clock (SMC), Stratum 4 Enhanced and Stratum 4 2. Telcordia GR-253-CORE September 2000 for SONET Internal Clocks 3. ANSI T1.101 (DS1) February 1994 for Stratum 3, Stratum 4 Enhanced and Stratum 4 4. ANSI T1.105.09-1996 for SONET Minimum Clocks (SMCs) 5. ITU-T G.813 August 1996 for Option1 and Option 2 clocks (with external jitter attenuator)
5.0
Applications
This section contains MT90401 application specific details for Master clock operation, LVDS output drivers setup, microport functionality and output clock phase adjustment.
5.1
Master Clock
In Freerun Mode, the frequency tolerance at the clock outputs is identical to the frequency tolerance of the source at the C20i input pin. Another consideration in determining the accuracy of the master timing source is the desired capture range. The sum of the accuracy of the master timing source and the capture range of the MT90401 will always equal 52 ppm. For example, if the master timing source is 20 ppm, then the capture range will be 32 ppm.
5.2
TIE Correction (using PCCi)
When Primary Holdover Mode is entered for short time periods, TIE correction should not be enabled. This will prevent unwanted accumulated phase change between the input and output. For example, we can estimate phase accumulation for a case when ten Normal to Holdover to Normal sequential mode changes occur, with each Holdover entered for 2 s with TIE enabled. Each mode change could account for a phase shift as large as 250 ns. Thus, the accumulated phase could be as large as 2.9 us, and, the overall MTIE could be as large as 2.9 us.
23
Zarlink Semiconductor Inc.
MT90401
Phase hold = 0.02ppm x 2s = 40ns Phase state = 50ns + 200ns = 250ns Phase 10 = 10 x ( 250ns + 40ns ) = 2.9us * * * 0.02 ppm is the accuracy of Holdover Mode 50 ns is the maximum phase continuity of the MT90401 from Normal Mode to Holdover Mode
Data Sheet
200 ns is the maximum phase continuity of the MT90401 from Holdover Mode to Normal Mode (with or without TIE Corrector Circuit)
When the same ten Normal to Holdover to Normal mode changes occur with TIE disabled, the overall MTIE will only be 250 ns. There would be no accumulated phase change, since the input to output phase is re-aligned after every Holdover to Normal state change.
5.3
C155 clock generation and LVDS output drivers
The MT90401 provides a 155.52 MHz clock that is frequency locked to the internally generated 19.44 MHz clock. The locking of both clocks is achieved by the internal analog PLL that multiplies the 19.44 MHz clock eight times. This C155 clock is output on pins C155P and C155N in LVDS format. The LVDS offset voltage Vos is set by applying an external 1.25 V reference voltage to the Vref input (pin 33). This pin can be connected to a common 1.25 V voltage reference that may exist on the customer board or alternatively can be generated by a simple voltage divider as it is shown in Figure 13 - LVDS Voltage Offset Vos Generation Circuit. To ensure proper operation of LVDS drivers, the decoupling capacitor must be placed very close to the MT90401 package.
Figure 13 - LVDS Voltage Offset Vos Generation Circuit
5.4
Microport
If the HW pin is tied low, an 8 bit Motorola microprocessor may be used to control the PLL and report on the device status. In this case the control pins SONET/SDH, RSEL, MS1, MS2, FS1, FS2, and FLOCK are unused and they are replaced by the control bits SONET/SDH, RSEL, MS1, MS2, FS1, FS2, FLOCK. The input pin PCCi remains in use. The output pins LOCK, HOLDOVER, SECOOR, PRIOOR function whether the device is in microprocessor mode or hardware mode, but these signals are also available in Status Register 1. The microport provides additional functionality not available in hardware.
24
Zarlink Semiconductor Inc.
MT90401
5.5 Output Phase Adjustment
Data Sheet
Two control registers are available to program the output phase offset of the generated clocks. All 16.384 MHz derived outputs clocks, F16o, F80, F0o, C16o, C8o, C4o and C2o can be collectively shifted up to 125 microseconds with a step size of 60 nS with respect to the input reference by programming the Set Delay Word 1 and Set Delay Word 2 registers. Control and Status Registers Address (A6A5A4A3A2A1A0) 00H (Table 6) 01H (Table 7) 02H 03H 04H (Table 8) 05H 06H (Table 9) 07H (Table 10) 08H 09H 0AH 0BH 0CH 0DH Register Control Register 1 Status Register 1 Reserved Reserved Control Register 2 Reserved Set Delay Word 2 Set Delay Word 1 Reserved Reserved Reserved Reserved Reserved Reserved Read/ Write Function
Read/ RSEL, FS2, FS1, MS2, MS1, SONET/SDH Write FLOCK, TCLR Read PRIOOR, SECOOR, Only RSV, FLim, RSV, RSV Read Only Read Only Read/ E3/DS3/OC3, E3/DS3, RSV=0, Write RSV=0, RSV=0, RSV=0, RSV=0. Read Set all bits to zero. /Write Read/ RSV=0, RSV=0, RSV=0, RSV=0, Write C16OCNT10,C16OCNT9, C16OCNT8 Read/ C16OCNT7-0 Write Read/ Set all bits to zero. Write Read Only Read Only Read Only Read Only Read Only Table 5 - Register Map OffEn, RSV=0, LOCK, HOLDOVER,
25
Zarlink Semiconductor Inc.
MT90401
Control and Status Registers (continued) Address (A6A5A4A3A2A1A0) 0EH 0FH (Table 11) 10H Reserved Identification Word Reserved Register Read/ Write Read Only Read ID7-0 Only Read/ Set all bits to zero. Write Table 5 - Register Map (continued) Function
Data Sheet
Bit 7
Name RSEL
Functional Description Reference Select. A zero selects the PRI (primary) reference source as the input reference signal and a one selects the SEC (secondary) reference. Switching between reference clocks operating at 8 kHz, 1.544 MHz and 2.048 MHz can be done at any time and without any special setup procedures. However it is recommended that the switching of the 19.44 MHz references will be performed by forcing PLL temporary into Holdover mode (MS2,MS1=01) to prevent excessive phase accumulation in the internal controller. The PLL can be switched back to Normal mode (MS2,MS1= 00) 250 us after the new input reference has been selected. Frequency Select 2 - 1. These bits select which of four possible frequencies (8 kHz, 1.544 MHz, 2.048 MHz or 19.44 MHz) may be input to the PRI and SEC inputs. FS2 - 0, FS1 - 0 = 19.44 MHz FS2 - 0, FS1 - 1 = 8 kHz. FS2 - 1, FS1 - 0 = 1.544 MHz. FS2 - 1, FS1 - 1 = 2.048 MHz. When "19.44 MHz" reference clock option is selected, a loss of 19.44 MHz clock or a larger than 30000 ppm frequency deviation may create a frequency step exceeding 4.6 ppm upon return from Auto-Holdover mode. This may result in a lock time that is longer than normally guaranteed. Mode Select 2 - 1: These bits select the PLL state of operation. MS2 - 0, MS1 - 0 = Normal. MS2 - 0, MS1 - 1 = Holdover. MS2 - 1, MS1 - 0 = Freerun. MS2 - 1, MS1 - 1 = Reserved. SONET / SDH. Set to one to move the loop filter corner frequency to 70 millihertz and limit the phase slope to 885 ns per second as per SONET requirements. Set to zero to move the corner frequency to 1.1 Hz and limit the phase slope to 53 ns per 1.326 ms. Fast Lock. Set to one to allow the PLL to lock faster than normal to the input reference. During the time that FLOCK is one, the wander generation of the PLL is, of necessity, compromised. Set to zero for normal operation. Table 6 - Control Register 1 (Address 00H - Read/Write)
6-5
FS2-1
4-3
MS2-1
2
SONET/SDH
1
FLOCK
26
Zarlink Semiconductor Inc.
MT90401
Bit 0 Name TCLR Functional Description
Data Sheet
TIE Clear. Set to zero to clear the Time Interval Error correction circuit resulting in a realignment of output phase with input phase. When this bit is zero, the Time Interval Error correction circuit is disabled. When this bit is one, the Time Interval Error correction circuit will function normally. Table 6 - Control Register 1 (Address 00H - Read/Write) (continued)
Bit 7
Name PRIOOR
Functional Description Primary Out Of Range. A one indicates that the primary reference is off the PLL center frequency by more than 12 ppm. The measurement is done on a 1 second basis using a signal derived from the 20 MHz clock input on C20i. When the accuracy of the 20 MHz clock is 4.6ppm, the effective out of range limits of the PRIOOR signal will be +16.6 ppm to -7.4 ppm or +7.4 ppm to -16.6 ppm. Secondary Out of Range. A one indicates that the secondary reference is off the PLL center frequency by more than 12 ppm. The measurement is done on a 1 second basis using a signal derived from the 20 MHz clock input on C20i. When the accuracy of the 20 MHz clock is 4.6 ppm, the effective out of range limits of the PRIOOR signal will be +16.6 ppm to -7.4 ppm or +7.4 ppm to -16.6 ppm. Lock. This bit goes high when the PLL is in frequency lock to the input reference. Holdover. This bit goes high whenever the device is in Holdover mode. Reserved. Frequency Limit. This bit goes high whenever the reference frequency hits the input frequency offset tolerance of the PLL. This bit can flicker high in the event of large excursions of still tolerable input jitter. Reserved. Table 7 - Status Register 1 (Address 01H - Read Only)
6
SECOOR
5 4 3 2
LOCK HOLDOVER RSV FLim
1-0
RSV
Bit 7
Name E3DS3/OC3
Functional Description E3DS3/OC3 Selection. Set this bit to zero to enable the differential 155.52 MHz output clock on the C155N/C155P pins and cause the C34/C44 pin to output its nominal clock frequency divided by 4. Set this bit to one to disable the differential 155.52 MHz output clock on the C155N/C155P pins and cause the C34/C44 pin to output its nominal clock frequency. E3/DS3. Set this bit low to select a clock rate of 44.736 MHz for the C34/C44 pin. Set high to select a clock rate of 34.368 MHz for the C34/C44 pins. Reserved. Set to zero for normal operation. Table 8 - Control Register 2 (Address 04H - Read/Write)
6 5-0
E3/DS3 RSV
27
Zarlink Semiconductor Inc.
MT90401
Bit 7-4 3 2-0 Name RSV OffEn Reserved. Set to zero. Functional Description
Data Sheet
Offset Enable. Set high to enable a programmed phase shift between the input reference and the generated clocks.
C16OCNT10-8 C16 Offset Count. The three most significant bits of the offset delay word. These bits program the offset all clocks derived from 16.384 MHz with respect to the input reference in step sizes of 60 nS. Table 9 - Set Delay Word 2 (Address 06H - Read/Write)
Bit 7-0
Name C16OCNT 7-0
Functional Description C16 Offset Count. The eight least significant bits of the offset delay word. These bits program the offset of all clocks derived from 16.384 MHz with respect to the input reference in step sizes of 60 nS.
Table 10 - Set Delay Word 1 (Address 07H - Read/Write)
Bit 7- 0
Name ID7-0
Functional Description Identification Word 7-0. These bits contain the revision number of the part. Table 11 - Identification Word (Address 0FH - Read Only)
28
Zarlink Semiconductor Inc.
MT90401
Absolute Maximum Ratings* Parameter 1 2 3 4 5 Supply voltage Voltage on any pin Current on any pin Storage temperature 80 LQFP package power dissipation Symbol VDDR VPIN IPIN TST PPD -55 Min. -0.3 -0.3 Max. 7.0
Data Sheet
Units V V mA C mW
VDD+0.3 30 125 1000
* Voltages are with respect to ground (V SS) unless otherwise stated. * Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied.
Recommended Operating Conditions* Characteristics 1 Supply voltage 2 Operating temperature Sym. VDD TA Min. 3.0 -40 Typ. 3.3 25 Max. 3.6 +85 Units V 0 C
* Voltages are with respect to ground (V SS) unless otherwise stated.
DC Electrical Characteristics* Characteristics 1 2 3 4 5 6 7 8 9 10 11 12 13 Supply current with C20i = 0V Supply MHz current with C20i = 20 Sym. IDDS IDD VCIH VCIL IIL VOH VOL VOD dVOD VOS dVOS IOS TRF 300 1.15 250 2.4 0.4 460 40 1.35 40 20 600 0.7VDD 0.3VDD 15 Min. Max. 2 150 Units mA mA V V A V V mV mV V mV mA ps VCI55P = 0 or VC155N = 0 Measured at 20% and 80% VI=VDD or 0 V IOH= 10 mA IOL= 10 mA ZT = 100 W Conditions/Notes Outputs unloaded Outputs unloaded
CMOS high-level input voltage CMOS low-level input voltage Input leakage current High-level output voltage Low-level output voltage LVDS Differential Output Voltage LVDS Change in VOD between complementary output states LVDS Offset Voltage LVDS Change in VOS between complementary output states LVDS Output short circuit current LVDS Output Rise/Fall Times
* Voltages are with respect to ground (V SS) unless otherwise stated. * Supply voltage and operating temperature are as per Recommended Operating Conditions.
29
Zarlink Semiconductor Inc.
MT90401
AC Electrical Characteristics - Timing Parameter Measurement Voltage Levels* Characteristics 1 2 3 Threshold Voltage Rise and Fall Threshold Voltage High Rise and Fall Threshold Voltage Low Sym. VT VHM VLM CMOS 0.5VDD 0.7VDD 0.3VDD
Data Sheet
Units V V V
* Voltages are with respect to ground (V SS) unless otherwise stated. * Supply voltage and operating temperature are as per Recommended Operating Conditions. * Timing for input and output signals is based on the worst case
Timing Reference Points ALL SIGNALS tIF, tOF tIR, tOR V HM VT V LM
Figure 14 - Timing Parameter Measurement Voltage Levels
AC Electrical Characteristics - Microprocessor Timing* Characteristics 1 2 3 4 5 6 7 8 9 10 11 12 DS low DS High CS Setup R/W Setup Address Setup CS Hold R/W Hold Address Hold Data Delay Read Data Hold Read Data Setup Write Data Hold Write Sym. tDSL tDSH tCSS tRWS tADS tCSH tRWH tADH tDDR tDHR tDSW tDHW 0 10 Min. 30 30 0 18 0 0 4 10 50 30 Max. Units ns ns ns ns ns ns ns ns ns ns ns ns CL=150 pF Test Conditions
* Supply voltage and operating temperature are as per Recommended Operating Conditions.
30
Zarlink Semiconductor Inc.
MT90401
tDSH DS tCSS CS tRWS R/W tADS A0-A4 tDDR D0-D7 READ tDSW D0-D7 WRITE VALID DATA tDHW VALID DATA tDHR tADH tRWH tCSH tDSL
Data Sheet
VTT
VTT
VTT
VTT
VTT,VCT
VTT
Note: DS and CS may be connected together.
Figure 15 - Microport Timing
tR8D PRI/SEC 8kHz PRI/SEC 1.544MHz PRI/SEC 2.048MHz tR15D tRW tRW
tR2D
tRW
F8o NOTES: 1. Input to output delay values are valid after a TCLR or RST with no further state changes
Figure 16 - Input to Output Timing for T1/E1 signals (Normal Mode)
31
Zarlink Semiconductor Inc.
MT90401
tR19W PRI/SEC 19.44MHz C19o tR19D tR19W
Data Sheet
VT VT
Figure 17 - Input to Output Timing for 19.44 MHz Signal (Normal Mode)
AC Electrical Characteristics - Output Timing* Characteristics 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 Reference input pulse width high or low (8 KHz, 1.544 MHz, 2.048 MHz) Reference input pulse width high or low (19.4 MHz) Reference input rise or fall time 8 kHz reference input to F8o delay 1.544 MHz reference input to F8o delay 2.048 MHz reference input to F8o delay 19.44 MHz reference input to C19o delay F8o to F0o delay F8o to F16o delay F8o to C1.5o delay F8o to C6o delay F8o to C2o delay F8o to C4o delay F8o to C8o delay F8o to C16o delay C1.5o pulse width high or low C6o pulse width high or low C2o pulse width high or low C4o pulse width high or low C8o pulse width high or low C16o pulse width high or low C19o pulse width high or low C19o to c155 delay F0o pulse width low F8o pulse width high Sym. tRW tR19W tIR,tIF tR8D tR15D tR2D tR19D tF0D tF16D tC15D tC6D tC2D tC4D tC8D tC16D tC15W tC6W tC2W tC4W tC8W tC16W tC19W tC155D tF0WL tF8WH -85 400 220 38 115 23 -100 58 -6 -6 -6 -6 315 70 235 115 53 24 9 0 235 115 6 250 130 Min. 100 10 10 -65 425 230 42 125 35 -85 70 5 5 5 5 Max. Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Conditions/Notes
32
Zarlink Semiconductor Inc.
MT90401
AC Electrical Characteristics - Output Timing* (continued) Characteristics 26 27 28 29 30 31 32 33 F16o pulse width low Output clock and frame pulse rise or fall time Input Controls Setup Time Input Controls Hold Time C34o Pulse width low or high C44o Pulse width low or high C8.5o Pulse width low C11o Pulse width low Sym. tF16WL tOR,tOF tS tH tC34W tC44W tC8.5WL tC11WL 100 100 9 6 106 81 Min. 55 Max. 63 9 Units ns ns ns ns ns ns ns ns
Data Sheet
Conditions/Notes
* Supply voltage and operating temperature are as per Recommended Operating Conditions
tF8WH F8o tF0WL F0o tF16WL F16o tC16WL C16o tC8W C8o tC4W C4o tC2W C2o tC6W C6o tC15W tC6W tC6D VT tC2D VT tC4W tC4D VT tC8W tC8D VT tF16D VT tF0D VT VT
tC16D
VT
tC15D VT
C1.5o
Figure 18 - Output Timing 1
33
Zarlink Semiconductor Inc.
MT90401
tC19W C19o tC155D C155p C155n tC155D tC19W
Data Sheet
VT VLVH VLVL
Figure 19 - Output Timing 2
F8o MS1,2, RSEL, PCCi tS tH
VT
VT
Figure 20 - Input Controls Setup and Hold Timing
C34o
VT
tC44W C44o VT
tC 8.5 VT C8.5o
tC11 VT C11o
Figure 21 - Output Timing 3
34
Zarlink Semiconductor Inc.
MT90401
AC Electrical Characteristics - C20i Master Clock Input* Characteristics 1 2 3 Duty cycle Rise time Fall time Sym. Min. 40 Max. 60 10 10 Units % ns ns
Data Sheet
Conditions/Notes
* Supply voltage and operating temperature are as per Recommended Operating Conditions.
Performance Characteristics: Mode Switching* Characteristics 1 2 3 4 5 6 7 8 9 10 11 12 13 14 Phase lock time Output phase continuity with: reference switch mode switch to Normal mode switch to Freerun mode switch to Holdover Output phase slope - SDH mode - SONET mode Reference input for Auto-Holdover with: 8kHz -30k -30k -30k -30k 1.544MHz 2.048MHz 19.44MHz Capture range with C20i at: Holdover Mode accuracy with C20i at: 0ppm 20ppm 0ppm 20ppm Min. -0.02 -0.02 -52 -32 100 200 200 200 50 40 885 +30k +30k +30k +30k Typ. Max. +0.02 +0.02 +52 +32 Units ppm ppm ppm ppm s ns ns ns ns us/s ns/s ppm ppm ppm ppm 53 ns per 1.326 ms 4.6 ppm frequency offset Conditions/Notes
* Supply voltage and operating temperature are as per Recommended Operating Conditions.
Performance Characteristics: Output Jitter Generation - Filtered Characteristics 1 2 3 4 5 6 7 8 Intrinsic jitter at C1.5o (1.544 MHz) Intrinsic jitter at C2o (2.048 MHz) Intrinsic jitter at C19o (19.44 MHz) Intrinsic jitter at C19o (19.44 MHz) Intrinsic jitter at C34o (34.368 MHz) Intrinsic jitter at C34o (34.368 MHz) Intrinsic jitter at C44o (44.736 MHz) Intrinsic jitter at C44o (44.736 MHz) MAX UIpp 0.004 0.004 0.100 0.100 0.044 0.039 0.044 0.037 MAX ns-pp 2.76 1.83 5.20 5.16 1.30 1.15 0.99 0.82 Notes Filter: 10 Hz - 40 kHz Filter: 20 Hz - 100 kHz Filter: 500 Hz - 1.3 MHz OC-3 Filter: 65 kHz - 1.3 MHz OC-3 Filter: 100 Hz - 800 kHz Filter: 10 kHz - 800 kHz Filter: 10 Hz - 400 kHz Filter: 30 kHz - 400 kHz
* Supply voltage and operating temperature are as per Recommended Operating Conditions.
35
Zarlink Semiconductor Inc.
MT90401
Data Sheet
Performance Characteristics: Output Jitter Generation - Filtered (VDD = 3.3V +/- 10%, TA = -5C to +85C) Characteristics 1 2 3 4 Intrinsic jitter at C155o (155.52 MHz) Intrinsic jitter at C155o (155.52 MHz) Intrinsic jitter at C155o (155.52 MHz) Intrinsic jitter at C155o (155.52 MHz) MAX UIpp 0.12 0.11 0.18 0.13 MAX ns-pp 0.76 0.69 1.13 0.83 Notes Filter: 100 Hz - 400 kHz OC-1 Filter: 20 kHz - 400 kHz OC-1 Filter: 500 Hz - 1.3 MHz OC-3 Filter: 65 kHz - 1.3 MHz OC-3
Performance Characteristics: Output Jitter Generation - Unfiltered* Characteristics 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Intrinsic jitter at C1.5o (1.544 MHz) Intrinsic jitter at C2o (2.048 MHz) Intrinsic jitter at C4o (4.096 MHz) Intrinsic jitter at C6o (6.312 MHz) Intrinsic jitter at C8o (8.192 MHz) Intrinsic jitter at C8.5o (8.592 MHz) Intrinsic jitter at C11o (11.184 MHz) Intrinsic jitter at C16o (16.384 MHz) Intrinsic jitter at C19o (19.44 MHz) Intrinsic jitter at C34o (34.368 MHz) Intrinsic jitter at C44o (44.736 MHz) Intrinsic jitter at C155o (155.52 MHz) Intrinsic jitter at F0o (8 kHz) Intrinsic jitter at F8o (8 kHz) Intrinsic jitter at F16o (8 kHz) Sym. MAX UIpp 0.010 0.012 0.027 0.037 0.048 0.032 0.036 0.096 0.11 0.12 0.12 0.21 NA NA NA MAX ns-pp 6.5 5.8 6.5 5.8 5.9 3.8 3.2 5.8 5.6 3.5 2.6 1.3 4.7 4.0 3.1 Notes
* Supply voltage and operating temperature are as per Recommended Operating Conditions.
36
Zarlink Semiconductor Inc.
For more information about all Zarlink products visit our Web Site at
www.zarlink.com
Information relating to products and services furnished herein by Zarlink Semiconductor Inc. or its subsidiaries (collectively "Zarlink") is believed to be reliable. However, Zarlink assumes no liability for errors that may appear in this publication, or for liability otherwise arising from the application or use of any such information, product or service or for any infringement of patents or other intellectual property rights owned by third parties which may result from such application or use. Neither the supply of such information or purchase of product or service conveys any license, either express or implied, under patents or other intellectual property rights owned by Zarlink or licensed from third parties by Zarlink, whatsoever. Purchasers of products are also hereby notified that the use of product in certain ways or in combination with Zarlink, or non-Zarlink furnished goods or services may infringe patents or other intellectual property rights owned by Zarlink. This publication is issued to provide information only and (unless agreed by Zarlink in writing) may not be used, applied or reproduced for any purpose nor form part of any order or contract nor to be regarded as a representation relating to the products or services concerned. The products, their specifications, services and other information appearing in this publication are subject to change by Zarlink without notice. No warranty or guarantee express or implied is made regarding the capability, performance or suitability of any product or service. Information concerning possible methods of use is provided as a guide only and does not constitute any guarantee that such methods of use will be satisfactory in a specific piece of equipment. It is the user's responsibility to fully determine the performance and suitability of any equipment using such information and to ensure that any publication or data used is up to date and has not been superseded. Manufacturing does not necessarily include testing of all functions or parameters. These products are not suitable for use in any medical products whose failure to perform may result in significant injury or death to the user. All products and materials are sold and services provided subject to Zarlink's conditions of sale which are available on request.
Purchase of Zarlink's I2C components conveys a licence under the Philips I2C Patent rights to use these components in and I2C System, provided that the system conforms to the I2C Standard Specification as defined by Philips. Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc. Copyright Zarlink Semiconductor Inc. All Rights Reserved.
TECHNICAL DOCUMENTATION - NOT FOR RESALE

▲Up To Search▲

Price & Availability of MT90401AB1

	To Download MT90401AB1 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .